Path Comparison Unit For Determining Paths In A Trellis That Compete With A Survivor Path

ABSTRACT

A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 11/045,585, filed Jan. 28, 2005; and is related to U.S. patentapplication Ser. No. 10/853,087, entitled “Method and Apparatus forMultiple Step Viterbi Detection with Local Feedback,” filed on May 25,2004; each incorporated by reference herein.

FIELD OF THE INVENTION

The present invention relates generally to equalization, detection anddecoding techniques using the Soft-Output Viterbi Algorithm (SOVA).

BACKGROUND OF THE INVENTION

A magnetic recording read channel converts an analog read channel intoan estimate of the user data recorded on a magnetic medium. Read headsand magnetic media introduce noise and other distortions into the readsignal. As the information densities in magnetic recording increase, theintersymbol interference (ISI) becomes more severe as well. In readchannel chips, a Viterbi detector is typically used to detect the readdata bits in the presence of intersymbol interference and noise.

The Soft-Output Viterbi Algorithm (SOVA) is a well known technique forgenerating soft decisions inside a Viterbi detector. A soft decisionprovides a detected bit with a corresponding reliability. These softdecisions can be used by an outer detector to improve the error rateperformance of the overall system. For a more detailed discussion ofSOVA detectors, see, for example, J. Hagenauer and P. Hoeher, “A ViterbiAlgorithm with Soft-decision Outputs and its Applications,” IEEE GlobalTelecommunications Conference (GLOBECOM), vol. 3, 1680-1686 (November1989). SOVA architectures exist for one-step trellises, where one softdecision is generated per clock cycle. SOVA detectors may beimplemented, for example, in next-generation read channel systems, anddata rates in excess of 2 Gigabits-per-second will have to be achieved.It is challenging to achieve such high data rates with existing SOVAarchitectures that consider one-step trellises.

A need therefore exists for a method and apparatus for performing SOVAdetection at the high data rates that are required, for example, byevolving high-end storage applications. A further need exists for amethod and apparatus for performing SOVA detection employing amultiple-step trellis.

SUMMARY OF THE INVENTION

Generally, a path comparison unit is disclosed for determining paths ina trellis that compete with a survivor path. The disclosed pathcomparison unit comprises a first type functional unit comprising amultiplexer and a register to store one or more survivor bits associatedwith the survivor path; and at least two second type functional units,wherein each second type functional unit comprises a multiplexer and alogical circuit to compute at least one equivalence bit indicatingwhether the bit for a respective path and the bit for the survivor pathare equivalent. Generally, the respective path is one or more of awin-lose path and a lose-win path. A plurality of the first typefunctional units can be connected in a register exchange architecture.

A functional element comprises the first type functional unit and thetwo second type functional units comprise. In one embodiment, the firsttype functional unit and the two second type functional units within afunctional element operate in parallel. The logical circuit, such as anexclusive OR (XOR) function, can compare an output of two multiplexersin the same functional element. A plurality of the functional elementsare connected according to the trellis.

A plurality of the functional elements can be configured in an arraystructure having a plurality of rows and a plurality of columns. In oneembodiment, an output of one of the first type functional units in afirst column is applied as an input to at least one functional elementin a subsequent column. A row in the array structure can correspond to agiven state and a column in the array structure can correspond to aone-step-trellis period.

Inputs to a given multiplexer comprise at least one survivor bit from atleast one functional element of a previous column. The multiplexers inthe first type functional units in a given row of the array structureare typically controlled by the same selection signal. In oneembodiment, at least two second type functional units in a given row ofthe array structure comprise first and second multiplexers operating inparallel and wherein the first multiplexers in the given row arecontrolled by a first selection signal and the second multiplexers inthe given row are controlled by a second selection signal. In oneimplementation, a first path comparison unit is provided for bitscorresponding to even one-step-trellis periods and a second pathcomparison unit is provided for bits corresponding to oddone-step-trellis periods.

According to another aspect of the invention, a circuit is disclosedthat comprises a first type functional unit comprising a multiplexer anda register; and at least two second type functional units, wherein eachsecond type functional unit comprises a multiplexer and a logicalcircuit, wherein (i) the first type functional unit and the at least twosecond type functional units operate in parallel, (ii) the multiplexersin the first type functional unit and the at least two second typefunctional units each process a same set of input signals, (iii) a firstlogical circuit in a first of the at least two second type functionalunits processes an output from a first multiplexer in the first of theat least two second type functional units and an output from themultiplexer in the first type functional unit; and (iv) a second logicalcircuit in a second of the at least two second type functional unitsprocesses an output from a second multiplexer in the second of the atleast two second type functional units and an output from themultiplexer in the first type functional unit.

A more complete understanding of the present invention, as well asfurther features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a one-step trellis diagram for a channel with memoryL=2;

FIG. 2 illustrates the two-step SOVA for the one-step trellis shown inFIG. 1;

FIG. 3 is a schematic block diagram for a SOVA implementation employinga one-step trellis;

FIG. 4 illustrates a one-step trellis for a channel with memory L=3;

FIG. 5 illustrates a two-step trellis for a channel with memory L=3;

FIG. 6 a schematic block diagram showing a SOVA implementation for atwo-step trellis;

FIG. 7 illustrates a detailed schematic block diagram of a SOVAimplementation for a two-step trellis;

FIG. 8 illustrates the path metric differences computed by a SOVAdetector for a two-step trellis;

FIG. 9 is a schematic block diagram showing an exemplary implementationof the ACS operation of FIG. 7 and the generation of path metricdifferences Δ⁻¹ and Δ₀;

FIG. 10 is a schematic block diagram showing an alternate implementationof the ACS operation of FIG. 7 and the generation of the path metricdifferences Δ⁻¹ and Δ₀;

FIG. 11 is a schematic block diagram showing an exemplary implementationof the survivor memory unit of FIG. 7;

FIG. 12 is a schematic block diagram showing an exemplary implementationof the path comparison of FIG. 7 for bits corresponding to evenone-step-trellis periods;

FIG. 13 is a schematic block diagram showing an exemplary implementationof the path comparison of FIG. 7 for bits corresponding to oddone-step-trellis periods; and

FIG. 14 is a schematic block diagram showing an exemplary implementationof the reliability update of FIG. 7 for the maximum-likelihood (ML)path.

DETAILED DESCRIPTION

The present invention recognizes that the limitation on achievable datarates in a SOVA detector is overcome by employing a multiple-steptrellis. The multiple-step trellis is obtained from a one-step trellisby collapsing transitions over multiple time steps into one. In otherwords, each transition in the multiple-step trellis corresponds tomultiple transitions in the one-step trellis. For example, in anexemplary two-step trellis, each transition in the two-step trelliscorresponds to two transitions in the original one-step trellis. SOVAdetectors in accordance with the present invention can operate at datarates that are about twice the data rates of conventional designs thatuse one-step trellises. Even larger speed-ups are achievable formultiple-step trellises with step sizes larger than two.

One-Step SOVA

The present invention is illustrated in the context of a two-step SOVA,where Viterbi detection is followed by reliability processing. For adiscussion of suitable two-step SOVA architectures for one-steptrellises, see, for example, O. J. Joeressen and H. Meyr, “A 40-Mb/sSoft-Output Viterbi Decoder,” IEEE J. Solid-State Circuits, vol. 30,812-818 (July, 1995), and E. Yeo et al., “A 500-Mb/s Soft-Output ViterbiDecoder,” IEEE Journal of Solid-State Circuits, vol. 38, 1234-1241(July, 2003). The present invention applies, however, to any SOVAimplementation, as would be apparent to a person of ordinary skill inthe art. For a discussion of suitable one-step SOVAs, see, for example,J. Hagenauer and P. Hoeher, “A Viterbi algorithm with Soft-DecisionOutputs and its Applications,” IEEE Global Telecommunications Conference(GLOBECOM), vol. 3, 1680-1686 (November, 1989), and O. J. Joeressen etal., “High-Speed VLSI Architectures for Soft-Output Viterbi Decoding,”Journal of VLSI Signal Processing, vol. 8, 169-181 (1994), incorporatedby reference herein. It is important to distinguish the terms “one-stepSOVA” and “two-step SOVA” from the term “multiple-step trellis.” Whilethe term “n-step SOVA” indicates the number of steps, n, required toperform Viterbi and reliability processing, the term “multiple-steptrellis” indicates a trellis obtained from a one-step trellis bycollapsing transitions over multiple time steps into one.

Two-Step SOVA for a One-Step Trellis

FIG. 1 shows a one-step trellis 100, where a state is defined by the twomost recent state bits b₀b⁻¹ and denoted as state(b₀b⁻¹). This trelliscorresponds e.g. to an ISI channel with memory L=2. The bit b₀ isassociated with the transition:

state(b ⁻¹ b ⁻²)→state(b ₀ b ⁻¹).

FIG. 2 illustrates the two-step SOVA for an expanded version 200 of thetrellis 100 shown in FIG. 1. The two-step SOVA is explained, e.g., in O.J. Joeressen and H. Meyr, “A 40 Mb/s Soft-Output Viterbi Decoder,” IEEEJournal of Solid-State Circuits, Vol. 30, 812-18 (July, 1995). The firststep of the two-step SOVA determines the maximum likelihood (ML) path210 in FIG. 2, in a similar manner to the conventional Viterbialgorithm. FIG. 2 illustrates the steady-state of the Viterbi algorithmat time step n=3, after the four survivor paths into all four states{state(b₃b₂)} have been determined. The starting state 250{state(b₀b⁻¹)} of the ML path 210 can be identified by a D-steptrace-back from the {state(b_(D)b_(D−1))} with the minimum path metric,where D is the path memory depth of the survivor memory unit. In theexample of FIG. 2, it is assumed that D=3.

In the second step of the two-step SOVA, the reliabilities for the bitdecisions along the ML path 210 terminating in the starting statestate(b₀b⁻¹) are updated. The reliability update depth is denoted by U.

Let b′₀, b′⁻¹, . . . denote the state bits for the ML path 210 thatterminates in the starting state state(b′₀, b′⁻¹). Also, let {tilde over(b)}₀, {tilde over (b)}⁻¹, . . . denote the state bits for thecompeting, losing path 230 in FIG. 2 that terminates in the startingstate, state({tilde over (b)}₀,{tilde over (b)}⁻¹)=state(b′₀, b′⁻¹).

The absolute path metric difference between the ML path 210 andcompeting path 230 into the starting state, state(b′₀, b′⁻¹), is denotedby Δ′₀. The U intermediate reliabilities for the bits b′₀, b′⁻¹, . . . ,b′_(−U+1) that are updated using Δ′₀ are denoted by R′_(0,0), R′_(−1,0),. . . , R′_(−U+1,0), respectively. The reliabilities are updatedaccording to following rule:

${{{initialization}\text{:}\mspace{14mu} R_{0,{- 1}}^{\prime}} = {+ \infty}},{i = 0},{- 1},\ldots \mspace{11mu},{{{- U} + {1\text{:}\mspace{14mu} R_{i,0}^{\prime}}} = \left\{ {{{\begin{matrix}{\min \left( {R_{i,{- 1}}^{\prime},\Delta_{0}^{\prime}} \right)} & {{{{if}\mspace{14mu} b_{i}^{\prime}} \neq {\overset{\sim}{b}}_{i,0}},} \\R_{i,{- 1}}^{\prime} & {{otherwise},}\end{matrix}R_{{- U} + 1}^{\prime}} = R_{{{- U} + 1},0}^{\prime}},} \right.}$

where R′_(−1,−1), R′_(−2,−1), . . . R′_(−U+1,−1) are the intermediatereliabilities that were updated in the previous clock cycle using thepath metric difference Δ′⁻¹ for the starting state state(b′⁻¹, b′⁻²),and R′_(−U+1) is the final reliability for bit b′_(U+1).

It can be seen from the updating formula that the reliability for bitb′₀ is first initialized to infinity (R′_(0,−1)=+∞). Then, as thestarting state 250 for the ML path 210 moves from state(b′₀, b′⁻¹) tostate(b′_(U−1), b′_(U−2)), and as corresponding absolute path metricdifferences Δ′₀ to Δ′_(U−1) become available, the reliability for bitb′₀ is updated U times by using either the previous reliability, if thebit b′₀ agrees with the bit of the respective competing path, or usingthe minimum of the path metric difference and previous reliability.

The updating of reliabilities is shown in FIG. 2 for U=3, where the MLpath 210 and competing path 230 merge into the starting state state(b′₀,b′⁻¹)=state(00), and the intermediate reliabilities R′_(0,0), R′_(−1,0),and R′_(−2,0) are updated based on the path metric difference Δ′₀ andthe respective intermediate reliabilities from the previous updatingprocedure, i.e. R′_(−1,−1) and R′_(−2,−1). In the example of FIG. 2,only R′_(−2,0) is updated by taking the minimum of R′_(−2,−1) and Δ′₀,as the bits b′⁻² and {tilde over (b)}_(−2,0) differ from each other.

SOVA Architecture for a One-Step Trellis

FIG. 3 is a schematic block diagram showing a SOVA detector for aone-step trellis 300 (referred to in the following as a one-step-trellisSOVA detector). As shown in FIG. 3, a one-step-trellis SOVA detector 300processes a received signal to generate soft decisions, in a well knownmanner. Each soft decision includes the detected bit and a correspondingreliability value. The SOVA detector 300 generates soft decisions at thesame rate, f_(s), at which the input signals are received, f_(R). For amore detailed discussion of the SOVA, see, for example, J. Hagenauer andP. Hoeher, “A Viterbi Algorithm with Soft-Decision Outputs and itsApplications,” IEEE Global Telecommunications Conference (GLOBECOM),vol. 3, 1680-1686 (November, 1989).

SOVA Detection at Higher Data Rates

FIG. 4 illustrates a one-step trellis 400 for an ISI channel having amemory L 3. There are eight channel states, and two branchescorresponding to the bits b_(n)=0 and b_(n)=1 leave each state,state(b⁻¹b⁻²b⁻³), to reach a respective successor state,state(b₀b⁻¹b⁻²).

As previously indicated, the present invention increases the maximumdata rate that may be achieved by a SOVA detector by transforming theoriginal one-step trellis 400 into a multiple-step trellis 500, shown inFIG. 5. FIG. 5 illustrates an exemplary two-step trellis 500 for an ISIchannel having a memory L=3, corresponding to the one-step trellis 400of FIG. 4, in accordance with the present invention. The trellises inboth FIGS. 4 and 5 are for the illustrative case that the channel memoryis equal to L=3. While the present invention is described using theexemplary two-step trellis 500 of FIG. 5, the invention generalizes tocases where more than two steps are processed at once in a multiple-steptrellis, as would be apparent to a person of ordinary skill in the art.As shown in FIG. 5, when one step is processed in the two-step trellis500, two steps from the original one-step trellis 400 are processed atonce. In this manner, if a two-step trellis is used, the maximum datarate that can be achieved in a hardware implementation is effectivelyincreased by a factor of about two compared to a one-step-trellisimplementation. A higher data rate increase can be achieved if more thantwo steps from the original one-step trellis are processed at once inthe multiple-step trellis.

SOVA Architecture for a Two-Step Trellis

FIG. 6 is a schematic block diagram showing a SOVA implementation for atwo-step trellis 600 (also referred to in the following as atwo-step-trellis SOVA detector) incorporating features of the presentinvention. As shown in FIG. 6, the serial received signal is convertedto a parallel signal at stage 610 and the parallel signals are processedby the two-step-trellis SOVA detector 600, for example, using theexemplary implementation discussed below in conjunction with FIG. 7. Thetwo-step-trellis SOVA detector 600 generates the detected bits andreliabilities at half the rate, f_(s)=½·f_(R), at which the inputsignals are received, f_(R). Thus, two soft decisions are generated perclock cycle. The parallel output of the two-step trellis SOVA detector600 may be converted to a serial signal at stage 650.

FIG. 7 illustrates a schematic block diagram of an exemplary two-stepSOVA architecture 700 for a two-step trellis incorporating features ofthe present invention. As shown in FIG. 7, the exemplary SOVAarchitecture 700 for a two-step trellis comprises a branch metric unit(BMU) 710.

The BMU 710 is explained for the two-step trellis shown in FIG. 5without loss of generality. The BMU 710 computes one-step-trellis branchmetrics, m(0000), m(0001), . . . , m(1111), as follows:

m(b ₀ b ⁻¹ b ⁻² b ⁻³)=[y−e(b ₀ b ⁻¹ b ⁻² b ⁻³)]²,

where the subtracted term e(b₀b⁻¹b⁻²b⁻³) is the ideal (noise-less)channel output under the condition that the state bit block (on whichthe ideal output depends) is b₀b⁻¹b⁻²b⁻³.

In each two-step-trellis clock cycle, each one-step-trellis branchmetric is used as a summand in two distinct two-step-trellis branchmetrics. The two-step-trellis branch metric for the 5 state bitsb₀b⁻¹b⁻²b⁻³b⁻⁴, where b₀ is the most recent bit at the laterone-step-trellis period of the two-step-trellis cycle, is given by:

m _(branch)(b ₀ b ⁻¹ b ⁻² b ⁻³ b ⁻⁴)=m(b ⁻¹ b ⁻² b ⁻³ b ⁻⁴)+m(b ₀ b ⁻¹ b⁻² b ⁻³).

In addition, the exemplary two-step-trellis SOVA architecture 700comprises an add-compare-select unit (ACSU) 900, discussed below inconjunction with FIGS. 9 and 10, a survivor memory unit (SMU) 1100,discussed below in conjunction with FIG. 11, a path comparison unit1200, discussed below in conjunction with FIGS. 12 and 13, a reliabilityunit 1400, discussed below in conjunction with FIG. 14, and a number ofdelay operators D1-D3.

The BMU 710, ACSU 900, and SMU 1100 implement the first step of thetwo-step SOVA, i.e., maximum-likelihood sequence detection using theViterbi algorithm. The second step of the two-step SOVA is implementedby the path comparison unit 1200, which computes the paths that competewith a respective win-win path, and the reliability update unit 1400,which updates the reliabilities for the ML path.

Path Metric Difference and ACS Decision Definitions

A conventional one-step-trellis SOVA implementation computes oneabsolute path metric difference per state at each (one-step-trellis)clock cycle, as described, e.g., in O. J. Joeressen and H. Meyr, “A 40Mb/s Soft-Output Viterbi Decoder,” IEEE Journal of Solid-State Circuits,Vol. 30, 812-18 (July, 1995). The present invention recognizes that inthe exemplary implementation for a two-step trellis, where two stepsfrom the original one-step trellis 400 are processed at once, two pathmetric differences are computed per state at each (two-step-trellis)clock cycle. Thus, as discussed below in conjunction with FIG. 9 andFIG. 10, the ACSU 900 generates, for each state, two path metricdifferences Δ⁻¹, and Δ₀ for the first and second period of the(two-step-trellis) clock cycle.

FIG. 8 illustrates the computation of the path metric differences Δ⁻¹and Δ₀ in a two-step-trellis SOVA detector 600 for the exemplaryone-step and two-step trellises 400 and 500, where n is theone-step-trellis time index and m is the two-step-trellis time index. Ina two-step-trellis SOVA implementation, each two-step-trellis cyclecontains two one-step-trellis periods. For example, as shown in FIG. 8,the cycle associated with the two-step-trellis index m=0 contains thetwo one-step-trellis periods associated with the one-step-trellisindices n=0 and n=−1. FIG. 8 shows four competing paths 810, 820, 830,840. Each path 810, 820, 830, 840 can be indentified with a respectivetwo-bit selection signal indicating whether the path wins or loses ineach one-step-trellis period of the two-step-trellis cycle into thestate that terminates in the state defined by the 3-bit blockb₀b⁻¹b⁻²=000. For example, the win-lose path 810 wins (relative to thelose-lose path) in the first period (n=−1) and loses (relative to thewin-win path) in the second period (n=0) of the two-step-trellis cycle.

FIG. 8 shows the four competing paths 810, 820, 830 and 840 thatterminate in the state defined by the 3-bit block b₀b⁻¹b⁻²=000.

The path metric difference Δ₀ for the second period of thetwo-step-trellis cycle, into the state associated with theone-step-trellis index n=0, is the difference between the win-win pathsegment 820-0 and the win-lose path segment 810-0. The path metricdifference Δ⁻¹ for the first period of the two-step-trellis cycle, intothe respective state associated with the one-step-trellis index n=−1, isthe difference between the win-win path segment 820-1 and the lose-winpath segment 830-1.

In a conventional one-step-trellis SOVA implementation, the ACSgenerates a single ACS decision, e, indicating, for each state, whichbranch to trace back along the winning path through the trellis.According to an exemplary convention, a value of e=0 provides anindication to trace back the upper branch from a state. The presentinvention recognizes that in a two-step-trellis SOVA implementation, theACS 900 needs to generate, for each two-step-trellis cycle, two-bit ACSdecisions ef, indicating, for each two-step-trellis cycle, whichbranches to trace back along the win-win path through the trellis, wheree corresponds to the first period and f to the second period of thetwo-step-trellis cycle. Thus, a two-bit ACS decision of ef=00 providesan indication to trace back the upper branches out of the state thatterminates in the state defined by the 3-bit block b₀b⁻¹b⁻²=000 throughthe trellis 800 along the win-win path 820 to the state defined by the3-bit block b⁻²b⁻³b⁻⁴=000.

Again, the path metric difference Δ₀ for the second period of thetwo-step-trellis cycle is the difference between the win-win pathsegment 820-0 and the win-lose path segment 810-0. Similarly, the pathmetric difference Δ⁻¹ for the first period of the two-step-trellis cycleis the difference between the win-win path segment 820-1 and thelose-win path segment 830-1. Thus, to compute the path metricdifferences, Δ₀ and Δ⁻¹, three different paths need to be distinguished(win-win path 820, win-lose path 810, and lose-win path 830). Thetwo-bit ACS decisions ef, however, only allows two of these paths to bedistinguished. The win-win path 820 can be identified using the two-bitACS decision ef=00. The lose-win path 830 can be identified using thetwo-bit selection signal e f=01, which can be derived from the ACSdecision by using e and inverting f ( f denotes the inversion of f).While the second win-lose path segment 810-0 can be identified in termsof the ACS decision e, i.e. by ē=1, the first win-lose path segment810-1 cannot be identified in terms of the ACS decision, f. Thus, inorder to sufficiently define the win-lose path 810 through the two-steptrellis, an additional selection signal F is generated, as discussedfurther below.

The best path, i.e., the win-win path 820 into state(b₀b⁻¹b⁻²) is givenby the bit sequence b₀b⁻¹b⁻²b⁻³b⁻⁴=b₀b⁻¹b⁻²ef=00000.

The lose-win-path 830 is thus the path that lost to the win-win path 820in the first period of the two-step-trellis cycle and then became partof the win-win path 820. This path 830 is given by the bit sequenceb₀b⁻¹b⁻²b⁻³b⁻⁴=b₀b⁻¹b⁻²e f=00001, and it can be traced back fromstate(b₀b⁻¹b⁻²) to state state(b⁻¹b⁻²e), and then from state(b⁻¹b⁻²e) tostate(b⁻²e f) using the ACS decision e and the inverted ACS decision f.The path metric difference Δ⁻¹ is defined as the path metric differencebetween the win-win path segment 820-1 and the lose-win path segment830-1.

The win-lose-path 810 is the winning path into state(b⁻¹b⁻²ē) and thelosing path into state(b₀b⁻¹b⁻²). Denote the one-step-trellis ACSdecision for the two paths into state state(b⁻¹b⁻²ē) by F. Then, thewin-lose-path 810 can be traced back from state(b₀b⁻¹b⁻²) tostate(b⁻¹b⁻²ē) and then to state(b⁻²ēF). In the example of FIG. 8, thewin-lose path 810 is given by the state sequenceb₀b⁻¹b⁻²b⁻³b⁻⁴=b₀b⁻¹b⁻²ēF=00010. The path metric difference Δ₀ isdefined as the path metric difference between the win-win path segment820-0 and win-lose path segment 810-0.

The lose-lose-path 840 can be traced back from state(b₀b⁻¹b⁻²) tostate(b⁻¹b⁻²ē) and state(b⁻² eF), but it is not of importance for thecomputation of the path metric differences Δ⁻¹ and Δ₀.

In summary, for each state(b₀b⁻¹b⁻²) two path metric differences Δ₁ andΔ₀ are computed, the former for the first period and the latter for thesecond period of a two-step-trellis cycle. The lose-win path 830 can betraced back from state(b₀b⁻¹b⁻²) to state(b⁻²e f) using the two-bitselection signal e f, and the win-lose path 810 can be traced fromstate(b₀b⁻¹b⁻²) to state(b⁻²ēF) using the two-bit selection signal ēF.

Returning to FIG. 7, the path metric differences Δ₀ and Δ⁻¹, and the ACSdecisions e, f and F are delayed in the delay buffers D2 for a time thatis equal to the delay of the path memory and the delay buffer D1. Thepath comparison unit 1200 generates, for each state and bit within thereliability update window, an equivalence bit that indicates whether thewin-win path and a respective competing path agree in terms of the bitdecision. The path metric differences and equivalence bits thatcorrespond to the starting state of the ML path are selected based on aselection signal that is defined by the state bits in the delay bufferD1. The state bits for the ML path at the output of SMU are first storedin the delay buffer D1 and then in the delay buffer D3.

ACSU

FIG. 9 is a schematic block diagram showing an exemplary implementationof the ACSU 900 of FIG. 7 and the generation of path metric differencesΔ⁻¹ and Δ₀ and the additional ACS decision F. The exemplary ACSU 900considers an 8-state two-step trellis with 4 transitions per state, suchas the trellis 500 shown in FIG. 5, in which each state is defined bythe past 3 state bits b₀b⁻¹b⁻². Each two-step-trellis branch metricm_(branch)(b₀b⁻¹b⁻²b⁻³b⁻⁴) depends on the 3 state bits b⁻²b⁻³b⁻⁴ thatdefine the starting state of a transition in the two-step trellis 800,and also on the 2 state bits b₀b⁻¹ that correspond to the pathextension. The path metric for above path extension is computed by:

m′ _(path)(b ₀ b ⁻¹ b ⁻² b ⁻³ b ⁻⁴)=m _(path)(b ⁻² b ⁻³ b ⁻⁴)+m_(branch)(b ₀ b ⁻¹ b ⁻² b ⁻³ b ⁻⁴),

where m_(path) (b⁻²b⁻³b⁻⁴) is the path metric for the winning path intostate state(b⁻²b⁻³b⁻⁴) at the previous two-step-trellis cycle.

For each state, the ACSU performs the ACS operation to determine thewinning path using a set of adders 910, a comparator 920 and a selector930. For example, for state(000), the four path metrics for the pathextensions into this state are computed as

m′ _(path)(00000)=m _(path)(000)+m _(hrate)(00000)

m′ _(path)(00010)=m _(path)(010)+m _(hrate)(00010)

m′ _(path)(00001)=m _(path)(001)+m _(hrate)(00001)

m′ _(path)(00011)=m _(path)(011)+m _(hrate)(00011)

The path metric for the winning path 820 into state(b₀b⁻¹b₂) isdetermined with a 4-way comparison 920 among the path metrics for the 4path extensions into this state, i.e., it is the minimum of the 4 valuesm′_(path)(b₀b⁻¹b⁻² 00), m′_(path)(b₀b⁻¹b⁻²10), m′_(path)(b₀b⁻¹b⁻²01),and m′_(path)(b₀b⁻¹b⁻² 11).

In the ACSU 900, the path metric differences Δ⁻¹ and Δ₀ are computedafter the two-step-trellis ACS operation, as shown in FIG. 9. Thetwo-bit, two-step-trellis ACS decision ef generated by the comparator920 is used to select the path metric for the winning path (alsoreferred to as the win-win path 820) at the selector 930 as in aconventional two-step-trellis ACSU. The path metric 940 of the lose-winpath 830 is chosen by a selector 950 using the 2-bit selection signal ef. The path metric difference Δ⁻¹ is computed by taking the absolutevalue of the difference between the path metric of the win-win path 820and lose-win path 830, as computed by a subtractor 955.

The win-lose path 810 and lose-lose path 840 are chosen using two 2-to-1multiplexers 960, 965, based on the selection signal ē. This isequivalent to selecting the win-lose and lose-lose path 840 using two4-to-1 multiplexers that are driven by the 2-bit selection signals ē0and ē1 respectively. The two selected path metrics are compared by acomparator 970 to identify the path metric 975 of the win-lose path 810,and the corresponding ACS decision F is generated. The path metric 975is selected by the selector 972. The path metric difference Δ₀ iscomputed by a subtractor 980 that computes the absolute value of thedifference between the path metric of the win-win path 820 and win-losepath 810.

FIG. 10 shows an alternate implementation of the ACS operation andgeneration of the path metric differences Δ⁻¹ and Δ₀. For each state,the ACSU 1000 performs the ACS operation to determine the winning pathusing a set of adders 1010, a set of comparators 1020, selection logicand a selector 1030. The path metric for the winning path 820 intostate(b₀b⁻¹b₂) is determined with six parallel concurrent two-waycomparisons 1020. For a more detailed discussion of the implementationof the ACS operation for multiple-step trellises using parallelconcurrent comparisons, see U.S. patent application Ser. No. 10/853,087,entitled “Method and Apparatus for Multiple-Step Viterbi Detection withLocal Feedback,” filed on May 25, 2004 and incorporated by referenceherein.

In the ACSU 1000, the path metric differences Δ⁻¹ and Δ₀ are selected orcomputed after the two-step-trellis ACS operation, as shown in FIG. 10.The two-bit, two-step-trellis ACS decision ef generated by the selectionlogic 1030 is again used to select the path metric for the winning path(also referred to as the win-win path 820) by a selector 1035 as in aconventional two-step-trellis ACSU. The path metric difference Δ⁻¹ isselected by a selector 1045 (controlled by selection logic 1040 thatprocesses the 2-bit ACS decision ef) that selects the output of theappropriate comparator 1020 that produced the absolute value of thedifference between the path metric of the win-win path 820 and lose-winpath 830.

Similarly, the path metric difference Δ₀ is selected by a selector 1055(controlled by selection logic 1050 that processes the first bit, e, ofthe 2-bit ACS decision ef and the selection signal F) that selects theoutput of the appropriate comparator 1020 that produced the absolutevalue of the difference between the path metric of the win-win path 820and win-lose path 810.

The ACS decision F is generated in the ACSU 1000 as follows. The pathmetric difference between the win-win path 820 and win-lose path 810 andthe path metric difference between the win-win-path 820 and thelose-lose path 840 are chosen using two selectors 1060, 1065, each ofwhich is controlled by selection logic that processes the 2-bit ACSdecision ef. The two selected path metric differences are compared by acomparator 1070 to generate the corresponding ACS decision F.

SMU

FIG. 11 is a schematic block diagram showing an exemplary implementationof the survivor memory unit 1100 of FIG. 7. Generally, the SMU 1100stores and updates the state bits for all 8 survivor paths using aconventional register-exchange architecture, where the multiplexers 1110are controlled by the two-bit, two-step-trellis ACS decision ef. FIG. 11shows the double row of the survivor memory unit 1100 that stores theodd and even state bits {circumflex over (b)}₀, {circumflex over (b)}⁻¹,{circumflex over (b)}⁻², {circumflex over (b)}⁻³, {circumflex over(b)}⁻⁴, {circumflex over (b)}⁻⁵, . . . along the survivor path intostate(b₀b⁻¹b⁻²)=state(000). The top row in the exemplary embodimentprocesses the predefined state bit b₀ and corresponding predefined statebits from other states, under control of the ACS decision ef, whereasthe bottom row processes the predefined state bit b⁻¹ and correspondingpredefined state bits from other states, under control of the ACSdecision ef. A double row structure similar to the one of FIG. 11 isimplemented for all 8 states. Per state and stored survivor bit pair,the SMU 1100 implements two multiplexers 1110 and two registers 1120 asa constituent functional unit. The SMU 1100 produces at the output thefinal survivor bits {circumflex over (b)}_(−D+2) and {circumflex over(b)}_(−D+1), where D is the path memory depth. In the exemplaryembodiment 1100, D=8. For a discussion of the register-exchange SMUarchitecture, see, e.g., R. Cypher and C. B. Shung, “GeneralizedTrace-Back Techniques for Survivor Memory Management in the ViterbiAlgorithm,” Journal of VLSI Signal Processing, 85-94 (1993).

The ML path 820 is the path with the overall minimum path metric. Thesurvivor bits {circumflex over (b)}_(−D+2) and {circumflex over(b)}_(−D+1) that correspond to the state with the overall minimum pathmetric are provided to the delay buffer D1 (FIG. 7) and denoted asb′_(−D+2) and b′_(−D+1). These bits are the state bits for the ML path820, and they both determine the starting state for the reliabilityupdate operation and also the final bit decisions.

Delay Buffers D1, D2, and D3

As previously indicated, the two-step-trellis SOVA architecture 700 ofFIG. 7 comprises a number of delay buffers D1-D3. The delay buffer D1delays the state bits at the end of the SMU 1100 that belong to the MLpath 820 by two two-step-trellis clock cycles. The final three bits ofthis buffer D1 define the starting state for the second step of thetwo-step SOVA. The starting state signal is used to select the pathmetric differences and equivalence bits for the ML path.

The ACS decisions e, f, F and the path metric differences Δ⁻¹, Δ₀ forall states are also delayed in the delay buffers D2. The delay of D2 isequal to the sum of the delay of the path memory and the buffer D1. Thedelay buffer D3 further delays the state bits that are outputted by thebuffer D1. The delay of D3 is equal to the delay of the reliabilityupdate unit.

Path Comparison Unit

As previously indicated, the path comparison unit 1200, shown in FIG. 12and FIG. 13, computes for each state the paths that compete with thesurvivor path, i.e., win-win path 820. In addition, the path comparisonunit 1200 generates, for each state and bit within the reliabilityupdate window, an equivalence bit that indicates whether the win-winpath 820 and a competing path agree in terms of the bit decision. InFIGS. 12 and 13, only the rows for state(b₀b⁻¹b⁻²)=state(000) are shown.

FIG. 12 is a schematic block diagram showing an exemplary implementationof the path comparison unit 1200-even for bits corresponding to evenone-step-trellis periods and FIG. 13 is a schematic block diagramshowing an exemplary implementation of the path comparison unit 1200-oddfor bits corresponding to odd one-step-trellis periods (collectivelyreferred to as the path comparison unit 1200). The path comparison unit1200 receives at each two-step-trellis cycle for each state the delayedACS decisions e, f and F, from which the selection signals ef, e f andēF are derived. The path comparison unit 1200 stores and updates thebits that correspond to all survivor paths. The path comparison unit1200 also computes equivalence bits for each surviving bit: anequivalence bit is 1 if the bit for the survivor path 820 and competingpath disagree, and 0 otherwise.

The survivor bits {circumflex over (b)}₀, {circumflex over (b)}⁻¹,{circumflex over (b)}⁻², {circumflex over (b)}⁻³, {circumflex over(b)}⁻⁴, {circumflex over (b)}⁻⁵, . . . are generated as shown in FIG. 12for even one-step-trellis periods and in FIG. 13 for oddone-step-trellis periods of a two-step-trellis cycle.

In FIGS. 12 and 13, the survivor bits of the win-lose path 810, whichare selected by ēF, and the survivor bits of the lose-win path 830,which are selected by e f, are compared to the survivor bits of thewin-win path 820, which are selected by ef, to generate correspondingequivalence bits. The path comparison unit 1200 resembles theregister-exchange implementation of the survivor memory unit 1100. Thebottom row of the path comparison units 1200-even, 1200-odd containregisters 1220 and multiplexers 1210 that store and select the survivorpaths for every state.

In addition, the top and middle rows of the path comparison units1200-even, 1200-odd contain two multiplexers 1210 per one-step-trellisperiod and state that select the bits of the competing lose-win path 830and win-lose path 810 using the selection signals e f and ēF,respectively, and there are two XOR gates that generate respectiveequivalence bits indicating whether the bit for the respective path (thelose-win path 830 or win-lose path 810 associated with the selectionsignals e f and ēF) and the bit for the winning (win-win) path areequivalent. The notation q_(−2,0) indicates the equivalence bit forsurvivor bit {circumflex over (b)}⁻² and path metric difference Δ′₀,while q_(−2,−1) indicates the equivalence bit for survivor bit{circumflex over (b)}⁻² and path metric difference Δ′⁻¹. Each column ofthe path comparison units 1200-even, 1200-odd corresponds to an even andodd one-step-trellis period, respectively.

A structure similar to the one shown in FIGS. 12 and 13 is required foreach state. While FIGS. 12 and 13 show a number of columns eachcontaining three multiplexers, two XOR gates and one register, the firstcolumn in FIG. 12 only includes two multiplexers, one XOR gate and oneregister, as it computes only one equivalence bit, i.e. q_(0,0), in theexemplary embodiment. The path comparison unit generates, for eachstate, equivalence bits up to q_(−U+2,−1), q_(−U+2,0) and q_(−U+1,−1),q_(−U+1,0), respectively, where U is the reliability update length. Inthe exemplary embodiment 1200, U=6.

Reliability Update Unit

FIG. 14 is a schematic block diagram showing an exemplary implementationof the reliability update unit 1400 of FIG. 7 that updates thereliabilities for the maximum-likelihood path 820. The exemplaryreliability update unit 1400 computes and stores two reliability valuesper two-step-trellis cycle.

Δ′⁻¹ and Δ′₀ are the delayed path metric differences for the ML path 820into the starting state (see FIG. 7). These two values are selectedamong the buffered path metric differences using the starting statesignal as shown in FIG. 7.

q′_(0,0), q′_(−1,−1), q′_(−1,0), q′_(−2,−1), q′_(−2,0), q′_(−3,−1),q′_(−3,0), . . . are the equivalence bits for the ML path into thestarting states state(b′⁻¹b′⁻²b′⁻³) and state(b₀b′⁻¹b⁻²). These signalsare selected among the equivalence bits computed in the path comparisonunit (see FIGS. 12 and 13) using the starting state signal as shown inFIG. 7.

The reliabilities R′_(0,0), R′_(−1,0), R′_(−2,0), R′_(−3,0), R′_(−4,0),R′_(−5,0), . . . are updated based on Δ′₀, whereas R′_(−1,−1),R′_(−2,−1), R′_(−3,−1), R′_(−4,−1), R′_(−5,−1) . . . are updated basedon Δ′⁻¹.

R_(max) is a hard-wired value and denotes the maximum reliability value,e.g., R_(max)=∞. The first reliabilities R′_(0,0) and R′_(−1,−1)consider R_(max) as an initialization value in the exemplary embodiment.

After initialization, a functional element, such as the exemplaryfunctional element 1410, comprises four functional units, such as theexemplary functional unit 1420, and two registers. Each functional unit1420 comprises a comparator, a multiplexer and an AND gate. The top rowof the reliability update unit 1400 computes reliability values for evenone-step-trellis periods and the bottom row computes reliability valuesfor odd one-step-trellis periods. For example, R′_(0,0) (computed in theprevious two-step-trellis cycle) and Δ′⁻¹ are used to computeR′_(−2,−1), under control of the corresponding equivalence bitq′_(−2,−1). Thereafter R′_(−2,−1) and Δ′₀ are used to compute R′_(−2,0)under control of the corresponding equivalence bit q′_(−2,0). Thus, twofunctional units operate in series to first compute R′_(−2,−1) and thenR′_(−2,0). In an analogous fashion, two functional units operate inseries to first compute R′_(−3,−1) and then R′_(−3,0), by using the pathmetric differences, Δ′⁻¹ and Δ′₀, and corresponding equivalence bits. Insummary, two groups of functional units operate in parallel to computethe reliability values R′_(−2,0) and R′_(−3,0) for the sametwo-step-trellis cycle, where each group comprises two functional unitsthat operate in series.

The reliability unit 1400 computes the final reliabilitiesR′_(−U+2)=R′_(−U+2,0) and R′_(−U+1)=R′_(−U+1,0), where U is thereliability update length. Soft decisions S′_(i) are generated based onthe final reliability values and corresponding bit decisions, e.g.according to the rule:

$S_{i}^{\prime} = \left\{ {\begin{matrix}R_{i}^{\prime} & {{{if}\mspace{14mu} b_{i}^{\prime}} \equiv 0} \\{- R_{i}^{\prime}} & {{{if}\mspace{14mu} b_{i}^{\prime}} \equiv 1}\end{matrix}.} \right.$

It is to be understood that the embodiments and variations shown anddescribed herein are merely illustrative of the principles of thisinvention and that various modifications may be implemented by thoseskilled in the art without departing from the scope and spirit of theinvention.

1. A path comparison unit that determines a plurality of paths in atrellis that compete with a survivor path in said trellis, comprising: afirst type functional unit comprising a multiplexer and a register tostore one or more survivor bits associated with said survivor path; andat least two second type functional units, wherein each second typefunctional unit comprises a multiplexer and a logical circuit to computeat least one equivalence bit indicating whether the bit for a respectivepath and the bit for said survivor path are equivalent.
 2. The pathcomparison unit of claim 1, wherein the respective path is one or moreof a win-lose path and a lose-win path.
 3. The path comparison unit ofclaim 1, wherein a plurality of said first type functional units areconnected in a register exchange architecture.
 4. The path comparisonunit of claim 1, wherein said first type functional unit and said twosecond type functional units comprise a functional element.
 5. The pathcomparison unit of claim 4, wherein the first type functional unit andthe two second type functional units within a functional element operatein parallel.
 6. The path comparison unit of claim 4, wherein saidlogical circuit compares an output of two multiplexers in the samefunctional element.
 7. The path comparison unit of claim 4, wherein aplurality of said functional elements are configured in an arraystructure having a plurality of rows and a plurality of columns.
 8. Thepath comparison unit of claim 7, wherein an output of one of said firsttype functional units in a first column is applied as an input to atleast one functional element in a subsequent column.
 9. The pathcomparison unit of claim 7, wherein a row in said array structurecorresponds to a given state.
 10. The path comparison unit of claim 7,wherein a column in said array structure corresponds to aone-step-trellis period.
 11. The path comparison unit of claim 7,wherein inputs to a given one of said multiplexers comprise at least onesurvivor bit from at least one functional element of a previous column.12. The path comparison unit of claim 7, wherein each multiplexer insaid first type functional units in a given row of said array structureis controlled by the same selection signal.
 13. The path comparison unitof claim 7, wherein said at least two second type functional units ingiven row of said array structure comprise first and second multiplexersoperating in parallel and wherein said first multiplexers in said givenrow are controlled by a first selection signal and said secondmultiplexers in said given row are controlled by a second selectionsignal.
 14. The path comparison unit of claim 7, wherein a plurality ofsaid functional elements in said array structure are connected accordingto said trellis.
 15. The path comparison unit of claim 1, wherein saidat least one equivalence bit is computed for at least one state and bitwithin a reliability update window.
 16. The path comparison unit ofclaim 1, further comprising a first path comparison unit for bitscorresponding to even one-step-trellis periods and a second pathcomparison unit for bits corresponding to odd one-step-trellis periods.17. The path comparison unit of claim 1, wherein said multiplexers arecontrolled by at least one selection signal based on anadd-compare-selection decision.
 18. The path comparison unit of claim 1,wherein survivor bits of a win-lose path and a lose-win path arecompared to survivor bits of said survivor path to generatecorresponding equivalence bits.
 19. The path comparison unit of claim 1,wherein said equivalence bits are provided to a reliability unit thatdetermines a reliability value for at least one bit decision.
 20. Thepath comparison unit of claim 1, wherein said logical circuit performsan exclusive OR (XOR) function.
 21. A circuit, comprising: a first typefunctional unit comprising a multiplexer and a register; and at leasttwo second type functional units, wherein each second type functionalunit comprises a multiplexer and a logical circuit, wherein (i) saidfirst type functional unit and said at least two second type functionalunits operate in parallel, (ii) said multiplexers in said first typefunctional unit and said at least two second type functional units eachprocess a same set of input signals, (iii) a first logical circuit in afirst of said at least two second type functional units processes anoutput from a first multiplexer in said first of said at least twosecond type functional units and an output from said multiplexer in saidfirst type functional unit; and (iv) a second logical circuit in asecond of said at least two second type functional units processes anoutput from a second multiplexer in said second of said at least twosecond type functional units and an output from said multiplexer in saidfirst type functional unit.
 22. The circuit of claim 21, wherein aplurality of said first type functional units are connected in aregister exchange architecture.
 23. The circuit of claim 21, whereinsaid logical circuit performs an exclusive OR (XOR) function.
 24. Thecircuit of claim 21, wherein a plurality of said circuits are configuredin an array structure having a plurality of rows and a plurality ofcolumns.
 25. The circuit of claim 24, wherein said first type functionalunit and said two second type functional units comprise a functionalelement and wherein an output of said first type functional unit isapplied to at least one functional element of a subsequent column. 26.The circuit of claim 24, wherein inputs to a given one of saidmultiplexers comprise at least one value from at least one circuit of aprevious column.
 27. The circuit of claim 24, wherein each multiplexerin said first type functional units in a given row of said arraystructure is controlled by the same selection signal.
 28. The circuit ofclaim 24, wherein said first multiplexers of said second type functionalunits in said given row are controlled by a first selection signal andsaid second multiplexers of said second type functional units in saidgiven row are controlled by a second selection signal.
 29. The circuitof claim 24, wherein a plurality of said circuits in said arraystructure are connected according to a trellis.